1. Field of the Invention
This invention generally relates to communication receivers and, more particularly, to a receiver calibration process that minimizes susceptibility to PVT variations.
2. Description of the Related Art
A typical receiver must be capable of capturing a signal with an unknown signal-to-noise ratio (SNR) and an unknown amplitude. As a result, the receiver must be capable of amplification and automatic gain control (AGC)—to set the gain to a specific amplitude. In a digital system, the receiver must also be capable of limiting—amplifying the received signal and converting it to a digital bit stream.
FIG. 1 is a schematic diagram of a conventional differential signal receiver (prior art). The first stage provides gain and improves SNR. The second stage provides frequency response conditioning. The third stage provides gain to enhance the signal amplitude.
Assuming that all transistors have the same small signal gain gm, all load resistors have the same resistance Rd (RD), and the source capacitance Cs is set to “0”, the low frequency gain of the receiver can be calculated to be:
  ADC  =            2      ⁢      gmRd        +          gmRd              1        +        gmRs            
Based on the models provided by the transistor manufacturer for their 40 nanometer (nm) process, the variation of the process parameters (min to max over process and temperature) is: gm 30%, R (Rd and Rs): 56%. Thus, the gm*R product varies by approximately 2× over process and temperature.
In applications where a limiting function is desired, the output of the receiver feeds a slicer, which converts the signal to a rail-to-rail digital bit stream. Therefore, there is a minimum DC gain requirement. Typically, the limiting receiver is designed to have a very high gain, in order to meet the minimum gain requirement over PVT variations.
Looking at the first stage, the output load forms a pole at:
      fp    ⁢                  ⁢    1    =      1          2      ⁢      π      *      RD      *      CL      ⁢                          ⁢      1      
Looking at the second stage, the RsCs degeneration forms a zero and a pole at:
            fz      ⁢                          ⁢      2        =          1              2        ⁢        π        *        Rs        *        Cs              ,            fp      ⁢                          ⁢      2        =                  1        +                  gm          ⁢                      Rs            2                                      2        ⁢        π        *        Rs        *        Cs            
And another pole at:
      fp    ⁢                  ⁢    3    =      1          2      ⁢      π      *      RD      *      CL      ⁢                          ⁢      2      
Looking at the third stage, the output load is forms a pole at:
      fp    ⁢                  ⁢    4    =      1          2      ⁢      π      *      RD      *      CL      ⁢                          ⁢      3      
CL is a combination of the gate capacitance of the nmos switch (Cgg) and the parasitic metal capacitance of the routing (Cp). Over process and temperature, Cgg can vary by 14% and Cp can vary by 50% (min to max).
Assuming that CL consists of 50% Cgg and 50% Cp, the location of the fp1, fp3, and fp4 poles can vary by up to 30%.
fz2 and fp2 are responsible for the frequency response shaping and are controlled by adjusting Cs. fz2 sets the amount of high frequency gain, while, if properly designed, fp2 is high enough not to interfere with the high frequency peaking. Its variation is not critical as long as it is placed at a very high frequency.
In summary, the variation of the poles and zero(s) of the receive filter make the frequency response unpredictable.
It would be advantageous if a receiver could be calibrated in a manner so as to make the transfer function stable, regardless of variations in process and temperature.